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DATA SHEET
256MB SDRAM Micro DIMM
EBS25UC8APMA (32M words x 64 bits, 1 bank)
Description
The EBS25UC8APMA is 32M words x 64 bits, 1 bank Synchronous Dynamic RAM Micro Dual In-line Memory Module (Micro DIMM), mounted 8 pieces of 256M bits SDRAM sealed in BGA package. This module provides high density and large quantities of memory in a small space without utilizing the surface mounting technology. Decoupling capacitors are mounted on power supply line for noise reduction. Note : Do not push the cover or drop the modules in order to protect from mechanical defects, which would be electrical defects.
Features
* Fully compatible with 8 bytes Micro DIMM: JEDEC standard outline * 144-pin socket type micro dual in line memory module (Micro DIMM) PCB height: 30.00mm (1.18inch ) Lead pitch: 0.50mm * 3.3V power supply * Clock frequency: 100MHz/133MHz (max.) * LVTTL interface * Data bus width: x 64 non-ECC * Single pulsed /RAS * 4 Banks can operates simultaneously and independently * Burst read/write operation and burst read/single write operation capability * Programmable burst length (BL): 1, 2, 4, 8, Full page * 2 variations of burst sequence Sequential Interleave * Programmable /CAS latency (CL): 2, 3 * Byte control by DQMB * Refresh cycles: 8192 refresh cycles/64ms * 2 variations of refresh Auto refresh Self refresh
Document No. E0241E30 (Ver. 3.0) Date Published May 2002 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2002
EBS25UC8APMA
Ordering Information
Part number EBS25UC8APMA-7A EBS25UC8APMA-75* EBS25UC8APMA-80 EBS25UC8APMA-7AL EBS25UC8APMA-75L* EBS25UC8APMA-80L Clock frequency MHz (max.) 133 133 100 133 133 100 /CAS latency Package 2, 3 3 2, 3 2, 3 3 2, 3 144-pin Micro DIMM Contact pad Gold Mounted devices EDS2508APSA
Note: 100MHz operation at /CAS latency = 2.
Pin Configurations
Front Side
1pin 2pin
143pin 144pin
Back Side
Front side Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Pin name VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 VSS DQMB0 DQMB1 VDD A0 A1 A2 VSS DQ8 DQ9 Pin No. 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 Pin name NC VSS NC NC VDD DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VDD A6 A8 VSS A9 A10 (AP)
Back side Pin No. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Pin name VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 VSS DQMB4 DQMB5 VDD A3 A4 A5 VSS DQ40 DQ41 Pin No. 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 Pin name CLK1 VSS NC NC VDD DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 DQ54 DQ55 VDD A7 BA0 VSS BA1 A11
Data Sheet E0241E30 (Ver. 3.0)
2
EBS25UC8APMA
Front side Pin No. 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 Pin name DQ10 DQ11 VDD DQ12 DQ13 DQ14 DQ15 VSS NC NC CLK0 VDD /RAS /WE /CS0 NC Pin No. 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 Pin name VDD DQMB2 DQMB3 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS SDA VDD Back side Pin No. 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 Pin name DQ42 DQ43 VDD DQ44 DQ45 DQ46 DQ47 VSS NC NC CKE0 VDD /CAS NC A12 NC Pin No. 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Pin name VDD DQMB6 DQMB7 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS SCL VDD
Pin Description
Pin name A0 to A12 Function Address input -- Row address A0 to A12 -- Column address A0 to A9 Bank select address Data-input/output Chip select Row address asserted bank enable Column address asserted Write enable Byte input/output mask Clock input Clock enable Data-input/output for serial PD Clock input for serial PD Power supply Ground No connection
BA0, BA1 DQ0 to DQ63 /CS0 /RAS /CAS /WE DQMB0 to DQMB7 CLK0, CLK1 CKE0 SDA SCL VDD VSS NC
Data Sheet E0241E30 (Ver. 3.0)
3
EBS25UC8APMA
Serial PD Matrix
Byte No. 0 1 2 3 4 5 6 7 8 9 Function described Number of bytes used by module manufacturer Total SPD memory size Memory type Number of row addresses bits Number of column addresses bits Number of banks Module data width Module data width (continued) Module interface signal levels SDRAM cycle time at CL = 3 (highest /CAS latency) (-7A/7AL, -75/75L) (-80/80L) 10 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 1 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 0 0 1 0 80H 08H 04H 0DH 0AH 01H 40H 00H 01H 75H 80H 54H 60H 00H 82H 08H 00H 01H 8FH 04H 06H 01H 01H 00H 0EH 75H A0H 54H 60H 00H 0FH 14H 15ns 20ns 7.5ns 10ns 5.4ns 6ns Comments 128 bytes 256 bytes SDRAM 13 10 1 64 bits 0 LVTTL 7.5ns 8ns 5.4ns 6ns None. 7.8s x8 None. 1 CLK 1,2,4,8,F 4 2,3 0 0
SDRAM access from Clock at CL = 3 (highest /CAS latency) 0 (-7A/7AL, -75/75L) (-80/80L) 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1
11 12 13 14 15 16 17 18 19 20 21 22 23
Module configuration type Refresh rate/type SDRAM width Error checking SDRAM width SDRAM device attributes: minimum clock delay for back-toback random column addresses SDRAM device attributes: Burst lengths supported SDRAM device attributes: number of banks on SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: /CS latency SDRAM device attributes: /WE latency SDRAM device attributes SDRAM device attributes: General SDRAM cycle time at CL = 2 (2nd highest /CAS latency) (-7A/7AL) (-75/75L, -80/80L)
24
SDRAM access from Clock at CL = 2 0 (2nd highest /CAS latency) (-7A/7AL) (-75/75L, -80/80L) 0 0 Minimum row precharge time (-7A/7AL) (-75/75L, -80/80L) 0 0
25 to 26 27
Data Sheet E0241E30 (Ver. 3.0)
4
EBS25UC8APMA
Byte No. 28
Function described Row active to row active min (-7A/7AL, -75/75L) (-80/80L) /RAS to /CAS delay min (-7A/7AL) (-75/75L, -80/80L) Minimum /RAS pulse width (-7A/7AL, -75/75L) (-80/80L)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 1 1 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1 1 0 1 0 1 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0FH 10H 0FH 14H 2DH 30H 40H 15H 20H 08H 10H 15H 20H 08H 10H 00H 12H 78H B9H FAH 7FH FEH 00H
Comments 15ns 16ns 15ns 20ns 45ns 48ns 256MB 1.5ns 2ns 0.8ns 1ns 1.5ns 2ns 0.8ns 1ns
29
30
31 32
Density of each bank on module Address and command signal input setup time (-7A/7AL, -75/75L) (-80/80L) Address and command signal input hold time (-7A/7AL, -75/75L) (-80/80L) Data signal input setup time (-7A/7AL, -75/75L) (-80/80L) Data signal input hold time (-7A/7AL, -75/75L) (-80/80L)
33
34
35
36 to 61 62 63
Superset information SPD data revision code Checksum for Bytes 0 to 62 (-7A/7AL) (-75/75L) (-80/80L)
1.2
64 to 65 66 67 to 71 72 73 to 90 91 to 92 93 to 94 95 to 98
Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location Manufacturer's part number Revision code Manufacturing date Assembly serial number
Continuation code Elpida Memory
99 to 127 Manufacturer specific data
Data Sheet E0241E30 (Ver. 3.0)
5
EBS25UC8APMA
Block Diagram
/CS0 /WE DQMB0 /CS DQMB1 /CS
D0
8 N0, N1 DQ0 to DQ7 DQ8 to DQ15 8 N8, N9
D1
DQMB2
/CS
DQMB3
/CS
D2
8 N2, N3 DQ16 to DQ23 DQ24 to DQ31 8 N10, N11
D3
DQMB4
/CS
DQMB5
/CS
D4
8 N4, N5 DQ32 to DQ39 DQ40 to DQ47 8 N12, N13
D5
DQMB6
/CS
DQMB7
/CS
D6
8 N6, N7 DQ48 to DQ55 DQ55 to DQ64 8 N14, N15
D7
/RAS /CAS A0 to A12 BA0 BA1 CKE0 CLK0 VDD
C100 to C118
/RAS (D0 to D7) /CAS (D0 to D7) A0 to A12 (D0 to D7) BA0 (D0 to D7) BA1 (D0 to D7) CKE (D0 to D7) CLK (D0 to D7) VDD (D0 to D7) VSS (D0 to D7) 10 SCL
Serial PD SCL A0 A1 A2 U0 SDA SDA
VSS CLK1 10pF
VSS Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. * D0 to D7: 256M bits SDRAM U0: 2k bits EEPROM C100 to C118: 0.1F N0 to N15: Network resistors (10)
Data Sheet E0241E30 (Ver. 3.0)
6
EBS25UC8APMA
Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 100 s and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VDD IOS PD TA Tstg Value -0.5 to VDD + 0.5 ( 4.6 (max.)) -0.5 to +4.6 50 8 0 to +70 -55 to +125 Unit V V mA W C C 1 Note
Notes: 1. SDRAM device specification Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = 0 to +70C) (SDRAM device specification)
Parameter Supply voltage Symbol VDD VSS Input high voltage Input low voltage VIH VIL min. 3.0 0 2.0 -0.3 max. 3.6 0 VDD + 0.3 0.8 Unit V V V V Note 1 2 3 4
Notes: 1. 2. 3. 4.
The supply voltage with all VDD pins must be on the same level. The supply voltage with all VSS pins must be on the same level. VIH (max.) = VDD + 2.0V for pulse width 3ns at VDD. VIL (min.) = VSS - 2.0V for pulse width 3ns at VSS.
Data Sheet E0241E30 (Ver. 3.0)
7
EBS25UC8APMA
DC Characteristics 1 (TA = 0 to +70C, VDD = 3.3V 0.3V, VSS = 0V)
Parameter Operating current Symbol ICC1 ICC1 ICC1 Standby current in power down Standby current in non power down Active standby current in power down Active standby current in non power down Burst operating current Refresh current ICC2P ICC2N ICC3P ICC3N ICC4 ICC5 ICC5 ICC5 Self refresh current Self refresh current (L-version) ICC6 ICC6 -XXL -7A/7AL -75/75L -80/80L Grade -7A/7AL -75/75L -80/80L max. 1040 880 855 24 160 32 240 1080 2000 1760 1700 24 8 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA VIH VDD - 0.2V VIL 0.2V 7 CKE = VIL, tCK = 12ns CKE, /CS = VIH, tCK = 12ns CKE = VIL, tCK = 12ns CKE, /CS = VIH, tCK = 12ns tCK = tCK (min.), BL = 4 tRC = tRC (min.) 6 4 1, 2, 6 1, 2, 4 1, 2, 5 3 Test condition Burst length = 1 tRC = tRC (min.) Notes 1, 2, 3
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output open condition 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, /CLK operating current. 7. After self refresh mode set, self refresh current.
DC Characteristics 2 (TA = 0 to +70C, VDD = 3.3V 0.3V, VSS = 0V)
Parameter Input leakage current Output leakage current Output high voltage Output low voltage Symbol ILI ILO VOH VOL min. -8 -1.5 2.4 -- max. 8 1.5 -- 0.4 Unit A A V V Test condition 0 VIN VDD 0 VOUT VDD DQ = disable IOH = -4mA IOL = 4mA Notes
Data Sheet E0241E30 (Ver. 3.0)
8
EBS25UC8APMA
Pin Capacitance (TA = +25C, VDD = 3.3V 0.3V)
Parameter Input capacitance Symbol CI1 CI2 CI3 CI4 CI5 CI6 Data input/output capacitance CI/O1 Pins Address /RAS, /CAS, /WE CKE /CS CLK DQMB DQ max. 25.0 23.0 23.0 23.0 23.0 5.0 6.0 Unit pF pF pF pF pF pF pF Notes
AC Characteristics (TA = 0 to +70C, VDD = 3.3V 0.3V, VSS = 0V) (SDRAM device specification)
-7A/7AL Parameter System clock cycle time (CL = 2) (CL = 3) CLK high pulse width CLK low pulse width Access time from CLK Data-out hold time CLK to Data-out low impedance CLK to Data-out high impedance Input setup time Input hold time Symbol min. tCK tCK tCH tCL tAC tOH tLZ tHZ tSI tHI 7.5 7.5 2.5 2.5 -- 2.7 1 -- 1.5 0.8 60 45 15 15 15 max. -- -- -- -- 5.4 -- -- 5.4 -- -- -- -75/75L min. 10 7.5 2.5 2.5 -- 2.7 1 -- 1.5 0.8 67.5 max. -- -- -- -- 5.4 -- -- 5.4 -- -- -- -80/80L min. 10 10 3 3 -- 2.7 1 -- 2 1 70 max. -- -- -- -- 6 -- -- 6 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns 1 1 1, 2 1, 2 1, 2, 3 1, 4 1 1 1 1 1 1 1 Notes 1
Ref/Active to Ref/Active command period tRC Active to Precharge command period Active command to column command (same bank) Precharge to active command period Write recovery or data-in to precharge lead time Last data into active latency Active (a) to Active (b) command period Transition time (rise and fall) Refresh period (8192 refresh cycles) tRAS tRCD tRP tDPL tDAL tRRD tT tREF
120000 45 -- -- -- 20 20 15
120000 48 -- -- -- 20 20 20
120000 ns -- -- -- ns ns ns
2CLK + -- 15ns 15 0.5 -- -- 5 64
2CLK + -- 20ns 15 0.5 -- -- 5 64
2CLK + -- 20ns 20 0.5 -- -- 5 64 ns ns ms 1
Notes: 1. 2. 3. 4.
AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V. Access time is measured at 1.4V. Load condition is CL = 50pF. tLZ (min.) defines the time at which the outputs achieves the low impedance state. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
Data Sheet E0241E30 (Ver. 3.0)
9
EBS25UC8APMA
Test Conditions * Input and output timing reference levels: 1.4V * Input waveform and output load: See following figures
2.4V 0.4V 2.0V 0.8V DQ CL tT
tT
Input Waveform and Output Load Relationship Between Frequency and Minimum Latency (SDRAM device specification)
Parameter Frequency (MHz) tCK (ns) /CAS latency Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data-in to precharge command (same bank) Active command to active command (different bank) Self refresh exit time Last data in to active command (Auto precharge, same bank) Self refresh exit to command input Precharge command to high impedance Last data out to active command (auto precharge) (same bank) Last data out to precharge (early precharge) Column command to column command Write command to data in latency DQM to data in DQM to data out CKE to CLK disable Register set to active command /CS to command disable Power down exit to command input Symbol lRCD lRC lRAS lRP lDPL lRRD lSREX lDAL lSEC lHZP lAPR lEP lCCD lWCD lDID lDOD lCLE lMRD lCDD lPEC -7A/7AL 133 7.5 CL = 2 2 8 6 2 2 2 1 4 8 2 1 -1 1 0 0 2 1 2 0 1 -75/75L 133 7.5 CL = 3 3 9 6 3 2 2 1 5 9 3 1 -2 1 0 0 2 1 2 0 1 -80/80L 10 10 CL = 2 2 7 5 2 2 2 1 4 7 2 1 -1 1 0 0 2 1 2 0 1 Notes 1 1 1 1 1 1 2 = [lDPL + lRP] = [lRC] 3
Notes: 1. IRCD to IRRD are recommended value. 2. Be valid [DESL] or [NOP] at next command of self refresh exit. 3. Except [DESL] and [NOP]
Data Sheet E0241E30 (Ver. 3.0)
10
EBS25UC8APMA
Pin Functions
CLK0, CLK1 (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge. /CS0 (input pin): When /CS is Low, the command input cycle becomes valid. When /CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS and /WE (input pins): Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command cycle CLK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0 and BA1 (BA) is precharged. BA0 and BA1 (input pin) BA0 and BA1 are bank select signal (BA). (See Bank Select Signal Table) [Bank Select Signal Table]
BA0 Bank 0 Bank 1 Bank 2 Bank 3 L H L H BA1 L L H H
Remark: H: VIH. L: VIL CKE0 (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down and clock suspend modes. DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the DQMB is Low, the output buffer becomes Low-Z. Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data is written. DQ0 to DQ63 (input/output pins): Data is input to and output from these pins. VDD (power supply pins): 3.3V is applied. VSS (power supply pins): Ground is connected.
Detailed Operation Part
Refer to the EDS2504APSA/08APSA/16APSA (E0228E).
Data Sheet E0241E30 (Ver. 3.0)
11
EBS25UC8APMA
Physical Outline
42.0 max. (38.0) 1.0 min. 1.0 min. 3.80 max.
Unit: mm
30.0
15.0
1
A 17.625 35.50 37.0 0.08 35.50 17.875 R1.0 0.1
2
B 0.80 0.08 0.875
4-R1.0 0.1
1.0 min.
Detail A
Detail B
0.50
4.0 0.1
Component area (back)
2.5 min.
0.625
1.0 min.
3.5 min.
3.5 min.
Component area (front)
5.0 0.1
0.37 0.03 1.0 0.08
0.25 max.
ECA-TS2-0028-01
Data Sheet E0241E30 (Ver. 3.0)
12
2.00 min.
EBS25UC8APMA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0202
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Data Sheet E0241E30 (Ver. 3.0)
13
EBS25UC8APMA
BGA is registered trademark of Tessera, Inc.
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0107
Data Sheet E0241E30 (Ver. 3.0)
14

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